A conventional example of this kind of circuit is shown in “SANYO TECHNICAL REVIEW,” Vol. 10, No. 1, February, 1978, page 32. However, this circuit is of the single-phase-comparator type (that is, it uses only one stage of a phase comparator). Thus, this circuit performs phase comparison only once during one period of the reference signal, resulting in a first disadvantage of having a short lock-up time (i.e., the time required to synchronize with the output signal).
A proposal to overcome this disadvantage is made in the Japanese Patent Application Laid-Open No. H10-135822. According to this publication, there are provided a reference signal generator that produces a plurality of reference signals having different phases from each other, a plurality of (for example, four) frequency dividers that divide the output signal of a voltage-controlled oscillator, and a plurality of phase comparators that compare the feedback signals from the individual frequency dividers with the corresponding reference signals.
The circuit according to the above publication, however, has a second advantage of consuming too much electric power. This second disadvantage has been found to stem from the provision of a plurality of frequency dividers. If further reduction of the lock-up time is attempted by performing phase comparison 16 times during one period of the reference signal, it is necessary to use 16 frequency dividers, leading to higher electric power consumption.
Moreover, the use of a plurality of frequency dividers, which each occupy a considerably large space, makes the device as a whole large, expensive, and difficult to fabricate in the form of an LSI. This is a third disadvantage.
A proposal to overcome these disadvantages is made in Japanese Patent Application Laid-Open No. 2001-267918. According to this publication, a first and a second variable frequency divider output a first and a second feedback signal, respectively. However, while these feedback signals are being output simultaneously, the outputs of phase comparators to which those feedback signals are fed interfere with each other, causing unlocking (the phenomenon in which the output signal that is coming into phase suddenly deviates from the preset frequency). This is a fourth disadvantage.
Moreover, the second variable frequency divider performs frequency division by a division factor equal to the integer part of N/n (where N and n are integers). (This is because a variable frequency divider that performs frequency division by a division factor containing a fraction has the disadvantages of being expensive and operating unstably.) Performing frequency division by a division factor equal to the integer part as described above, the second variable frequency divider produces an error from the ideal feedback signal that would be obtained if frequency division was performed by a division factor of exactly N/n. Accordingly, a phase comparator PC2 connected to the second variable frequency divider outputs a phase comparison signal that contains that error (in the present specification, such a signal is called an error signal). As a result, the output signal has a frequency deviated from the preset frequency. This is a fifth disadvantage.
Furthermore, by the use of the first and second variable frequency dividers, phase comparison is performed a plurality of times. This requires that an up counter, a decoder, an OR circuit, an AND circuit, and other circuits be provided between the output side of the second variable frequency divider and the phase comparator PC2, resulting in a complicated circuit configuration. This is a sixth disadvantage.